1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a capacitor used in DRAM having a vertical gate.
2. Description of the Related Art
As long as the trend for forming highly integrated circuit continues, methods capable of forming devices having smaller dimensions must be developed. Right now, semiconductor devices having sub-micron line width are being manufactured. In the past, the means to increase the packing density of integrated circuit devices have included the reduction of structural dimensions. For a DRAM capacitor, that means a reduction of the surface area of its electrode. However, by so doing, the amount of electric charges that can be stored in the capacitor is greatly reduced.
In general, the amount of stored charges within a DRAM capacitor must be above a certain threshold level so that the stored data can be retrieved correctly. When some of the dimensions of a DRAM capacitor are reduced, the maximum amount of stored charges capable of being stored by the capacitor drops correspondingly. Furthermore, as the charge-storing capacity of the capacitor drops, frequency of refreshes necessary for compensating the lost charges due to current leakage must be increased. Constant refreshes compromise a data processing speed of the DRAM. Hence, a method to reduce the area occupation of a capacitor on a semiconductor substrate without decreasing its storage capacity is one major issue for design engineers.
FIGS. 1A through 1C are schematic, cross-sectional diagrams used to depict steps in a conventional method for fabricating a capacitor.
Referring to FIG. 1A, a shallow trench isolation structure 102, a gate oxide layer 104 and a gate 106 are formed on a substrate 100. A source/drain region 108 is formed in the substrate 100. An oxide layer 110 is formed over the substrate 100. A contact opening 112 is formed in the oxide layer 110 to expose the source/drain region 108.
Referring to FIG. 1B, a conductive layer 114 is formed on the oxide layer 110 and fills the contact opening 112 to electrically couple with the source/drain region 108.
Referring to FIG. 1C, a photoresist layer (not shown) is formed on the conductive layer 114 to define a conductive region 114a. A hemispherical-grain silicon layer 115 is formed on the conductive region 114a. Thus a bottom electrode is formed. A dielectric layer 116 and a conductive layer 118 are formed in sequence on the hemispherical-grain silicon layer 115 to form a capacitor.
In the method mentioned above, the capacitor area shrinkage is limited by lithography limitation and alignment margin. Also, the bit line, the gate and the capacitor are all formed on the substrate, thus the area of each cell should be large enough for all necessary devices. Therefore, it is difficult to reduce the area of the cell. In other words, it is difficult to increase the integration of DRAM.